1. Field of the Invention
The present invention relates to a semiconductor device having a nonvolatile memory or a multiple power supply and, more particularly, to a method of fabricating a semiconductor device in which the thicknesses of gate oxide films below gate electrodes formed in a plurality of regions are different.
2. Description of the Related Art
FIG. 9 is a plan view showing a conventional semiconductor device having both an EPROM and a logic. As in FIG. 9, a semiconductor substrate of this semiconductor device 1 includes a first region constituting a cell region 10, a second region constituting a high-voltage power supply (HV) region 20 which supplies a high voltage of, e.g., 12.5 V, and a third region constituting a logic region 30 which operates at a power supply voltage of, e.g., 5 V.
The fabrication steps of this semiconductor device will be described below with reference to the sectional views of a semiconductor structure in the fabrication steps illustrated in FIGS. 26 to 35. First, a 550-nm thick field oxide film 3 for isolating element formation regions from each other is formed on the surface of a semiconductor substrate 2 made from, e.g., a silicon semiconductor, by using a LOCOS process. For this purpose, a mask is formed on the element formation regions on the semiconductor substrate 2, and heating is performed. As a result, the field oxide film 3 as an element isolation region is formed. The formation of the field oxide film 3 separates the semiconductor substrate 2 into the cell region 10, the HV region 20, and the logic region 30 (FIG. 26). Subsequently, a dummy oxide film 4 about 15 nm thick is formed on these element formation regions 10, 20, and 30 on the surface of the semiconductor substrate 2. Additionally, a photoresist 5 for covering the HV region 20 and the logic region 30 is formed on these regions 20 and 30.
By using this photoresist 5 as a mask, boron ions (llB.sup.+) 6 are implanted into the cell region 10 under the conditions of 60 keV and 3.times.10.sup.12 atoms/cm.sup.2 (FIG. 27). That is, ion implantation 6 into the channel region is done. Subsequently, the photoresist 5 is removed by an acid treatment in order to form a gate oxide film on the cell region 10. Thereafter, the dummy oxide film 4 on the element formation regions 10, 20, and 30 is etched away by a dilute HF treatment. This dilute HF treatment is accomplished by using a dilute HF solution containing NH.sub.4, HF, and H.sub.2 O. Consequently, the field oxide film 3 is also etched and as a result the thickness of the film 3 is decreased (FIG. 28). A gate oxide film 7 about 25 nm thick is then formed on the element formation regions 10, 20, and 30 on the semiconductor substrate 2 by thermal oxidation (FIG. 29). After the formation of the gate oxide film 7, a polysilicon layer 8 (to be referred to as a first polysilicon layer hereinafter) as a first layer is formed on the element formation regions and on the field oxide film by CVD (Chemical Vapor Deposition). In this first polysilicon film 8, an impurity such as phosphorus is thermally diffused. An insulating film 9 is formed on the first polysilicon film 8. This insulating film 9 is constituted by a three-layered film, i.e., an SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 film (ONO film) (FIG. 30).
Subsequently, the HV region 20 and the logic region 30 are exposed to the surface of the insulating film 9, and a photoresist 51 having a pattern which covers the cell region 10 is formed. The insulating film 9 is selectively etched away by using the photoresist 51 as a mask, and the HV region 20 and the logic region 30 of the first polysilicon film 8 are removed by using anisotropic etching such as RIE (Reactive Ion Etching). Thereafter, the exposed gate oxide film 7, i.e., portions of the gate oxide film 7 on the HV region 20 and the logic region 30 are etched away by the dilute HF treatment (FIG. 31). After the photoresist 51 is removed by the acid treatment, a dummy gate oxide film 11 about 15 nm thick is formed on the HV region 20 and the logic region 30 by thermal oxidation. Consequently, an oxide film 13 is also formed by the thermal oxidation on the side wall of the first polysilicon film 8 on the cell region 10. Thereafter, a photoresist 52 having a pattern which covers the cell region 10 and the logic region 30 and exposes the HV region 20 is formed on the semiconductor substrate 2. By using this photoresist 52 as a mask, boron ions (llB.sup.+) are implanted into a portion (the n-channel of HV) of the semiconductor substrate 2 below the dummy gate oxide film 11 in the HV region 20 under the conditions of 60 keV and 6.times.10.sup.12 atoms/cm.sup.2. That is, ion implantation 12 into the channel region is performed (FIG. 32).
Subsequently, the photoresist 52 is removed from the semiconductor substrate 2 by the acid treatment, and a photoresist 53 having a pattern which covers the cell region 10 and the HV region 20 and exposes the logic region 30 is formed on the semiconductor substrate 2. By using this photoresist 53 as a mask, boron ions (llB.sup.+) are first deeply implanted into a portion (the n-channel of 5 V) of the semiconductor substrate 2 below the dummy gate oxide film 11 in the logic region 30 under the conditions of 80 keV and 1.5.times.10.sup.12 atoms/cm.sup.2. Boron ions (llB.sup.+) are then shallowly implanted into the same portion under the conditions of 40 keV and 2.5.times.10.sup.12 atoms/cm.sup.2. That is, ion implantation 15 into the channel region is done (FIG. 33). After the photoresist 53 is removed by the acid treatment, a photoresist (not shown) which covers only the cell region 10 is formed. By using this photoresist as a mask, the dummy gate oxide film 11 is removed from the regions 20 and 30 by the dilute HF treatment. After the photoresist is removed by the acid treatment, a gate oxide film 14 about 18 nm thick is formed on the HV region 20 and the logic region 30. Note that the gate oxide film on the logic region 30 is not illustrated. A photoresist 54 which covers the cell region 10 and the HV region 20 is formed on the semiconductor substrate 2. By using this photoresist 54 as a mask, the gate oxide film 14 on the logic region 30 is removed by the dilute HF treatment (FIG. 34).
Finally, the photoresist 54 is removed by the acid treatment and the semiconductor substrate 2 is heated, forming a gate oxide film about 15 nm thick on the surfaces of the HV region 20 and the logic region 30. That is, in the HV region, a gate oxide film 16 about 25 nm thick is formed by stacking the oxide film on the gate oxide film 14. In the logic region 30, a gate oxide film 17 about 15 nm thick is formed by thermally oxidizing the surface of the semiconductor substrate. By this method, gate oxide films different in thickness are formed on the HV region 20 and the logic region 30. Thereafter, a polysilicon film (second polysilicon film) 18 as a second layer which serves as a gate electrode material is deposited on the entire surface of the semiconductor substrate 2 by the CVD process. As in the case of the first polysilicon film, an impurity such as phosphorus is diffused into this polysilicon film 18 (FIG. 35).
In such a conventional semiconductor device, for example, in a semiconductor device having both an EPROM and a logic, however, the gate electrodes in both the HV region and the logic region are made of the second polysilicon film. In addition, the gate oxide film thickness in the HV region is different from that in the logic region. Therefore, in the conventional fabrication method, a total of three oxide film removing steps using the dilute HF treatment are performed for the dummy gate oxide film in the cell, the gate oxide film in the cell, and the dummy oxide film in the HV region, before the gate oxide film in the HV region is formed. Furthermore, before the gate oxide film is formed in the logic region, removing of the gate oxide film in the HV region is performed in addition to the three-time dilute HF treatment; that is, the dilute HF treatment is performed a total of four times.
In the method of fabricating the conventional semiconductor device having both a memory and a logic as described above, the thickness of the field oxide film formed on the element isolation region is unavoidably decreased due to the dilute HF treatment performed a number of times in the oxide film removing steps. This decrease in the film thickness leads to a lowering or a variation in the field inverting voltage, causing leakage between the fields. In addition, a decrease in the field oxide film which is due to the film thickness decrease brings about a variation in the driving force of a transistor or leakage of the transistor. This causes a reduction in the yield of the products. In the prior art described above, it is desirable that the thickness of the field oxide film be 550 nm. However, the thickness is decreased to about 300 to 400 nm by the film thickness decrease caused by the dilute HF treatment performed a number of times.